A 14ns 1mb Cmos Sram With Variable Bit-organization
- 1 January 1988
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- A 25-ns 1-Mbit CMOS SRAM with loading-free bit linesIEEE Journal of Solid-State Circuits, 1987
- A 34-ns 1-Mbit CMOS SRAM using triple polysiliconIEEE Journal of Solid-State Circuits, 1987
- A 35-ns 128K×8 CMOS SRAMIEEE Journal of Solid-State Circuits, 1987
- 25-ns 256K×1/64K×4 CMOS SRAM'sIEEE Journal of Solid-State Circuits, 1986
- A reliable 1-Mbit DRAM with a multi-bit-test modeIEEE Journal of Solid-State Circuits, 1985
- A divided word-line structure in the static RAM and its application to a 64K full CMOS RAMIEEE Journal of Solid-State Circuits, 1983