SPEED: fast and efficient timing driven placement
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A new global router for row-based layoutPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Sequential circuit design using synthesis and optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Timing driven placement using complete path delaysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- RITUAL: a performance driven placement algorithmIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1992
- Benchmarks for layout synthesis---evolution and current statusPublished by Association for Computing Machinery (ACM) ,1991
- An analytic net weighting approach for performance optimization in circuit placementPublished by Association for Computing Machinery (ACM) ,1991
- Analytical placementPublished by Association for Computing Machinery (ACM) ,1991
- A New Symbolic Channel Router: YACR2IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Signal Delay in RC Tree NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983