A self-trimming 14-b 100-MS/s CMOS DAC
- 1 December 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 35 (12) , 1841-1852
- https://doi.org/10.1109/4.890297
Abstract
A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and dynamic linearity is presented. The DAC is based on a central core of 15 thermometer decoded MSBs, 31 thermometer decoded upper LSBs (ULSBs) and 31 binary decoded lower LSBs (LLSBs). The static linearity corresponding to the 14-b specification is obtained by means of a true background self-trimming circuit which does not use additional current sources to replace the current source being measured during self-trimming. The dynamic linearity of the DAC is enhanced by a special track/attenuate output stage at the DAC output which tracks the DAC current outputs when they have settled but attenuates them for a half-clock cycle after the switching instant. The DAC occupies 3.44 mm/spl times/3.44 mm in a 0.35-/spl mu/m CMOS process, and is functional at up to 200 MS/s, with best dynamic performance obtained at 100 MS/s. At 100 MS/s, power consumption is 180 mW from a 3.3-V power supply, and 210 mW at 200 MS/s.Keywords
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