A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC
- 1 January 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 34 (12) , 1708-1718
- https://doi.org/10.1109/4.808896
Abstract
No abstract availableKeywords
This publication has 13 references indexed in Scilit:
- A 14 b 100 Msample/s CMOS DAC designed for spectral performancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Mondriaan: a tool for automated layout synthesis of array-type analog blocksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Test structures for investigation of metal coverage effects on MOSFET matchingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 12-bit intrinsic accuracy high-speed CMOS DACIEEE Journal of Solid-State Circuits, 1998
- A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/IEEE Journal of Solid-State Circuits, 1998
- Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC'sIEEE Journal of Solid-State Circuits, 1997
- Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuitsIEEE Journal of Solid-State Circuits, 1993
- A 10-b 70-MS/s CMOS D/A converterIEEE Journal of Solid-State Circuits, 1991
- Characterisation and modeling of mismatch in MOS transistors for precision analog designIEEE Journal of Solid-State Circuits, 1986
- An 80-MHz 8-bit CMOS D/A converterIEEE Journal of Solid-State Circuits, 1986