Design of large embedded CMOS PLAs for built-in self-test
- 1 January 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 7 (1) , 50-59
- https://doi.org/10.1109/43.3129
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
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- Implementing a Built-In Self-Test PLA DesignIEEE Design & Test of Computers, 1985
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- A Design of Programmable Logic Arrays with Universal TestsIEEE Transactions on Computers, 1981
- A Hardware Approach to Self-Testing of Large Programmable Logic ArraysIEEE Transactions on Computers, 1981
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978