LATTIS: an iterative speedup heuristic for mapped logic
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Timing optimization of combinational logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Performance enhancement through the generalized bypass transformPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A heuristic algorithm for the fanout problemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Efficient techniques for timing correctionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Timing optimization on mapped circuitsPublished by Association for Computing Machinery (ACM) ,1991
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Synthesis and Optimization of Multilevel Logic under Timing ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Bounding Fan-out in Logical NetworksJournal of the ACM, 1984
- Parallel Prefix ComputationJournal of the ACM, 1980