Delay-fault test generation and synthesis for testability under a standard scan design methodology
- 1 January 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 12 (8) , 1217-1231
- https://doi.org/10.1109/43.238614
Abstract
No abstract availableThis publication has 13 references indexed in Scilit:
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