A Single-Chip 25pJ/bit Multi-Gigabit 60GHz Receiver Module

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Abstract
This paper presents the first single-chip 1.5 gigabit/s 60 GHz direct-conversion receiver. It consumes only 37 mW DC power (less than 25 pJ/bit) for a die size of only 3 mm times 1 mm. A three-stage front-end LNA, implemented in low-cost 0.15 mum silicon BiCMOS technology and utilizing a novel gain-boosting technique, shows a 24 dB measured gain with a 3.1 GHz 3-dB bandwidth with a DC power consumption of only 25 mW. A DC-biased-diode-based amplitude detector is integrated with the three-stage LNA in 3 mm times 1 mm for the direct down-conversion of the 60 GHz amplitude-modulated signal. The receiver chip is wire-bonded on a low-cost organic module with an integrated antenna. The measurement results show an excellent demodulation of 1.5 gigabit/s amplitude-modulated pseudo-random-binary-sequence up to a greater than 2 m distance from the transmitter. To the best knowledge of the authors, this fully integrated single chip (3 mm2) module solution, from antenna to demodulated baseband, exhibits the fastest transmitted data rate (1.5 Gbps) at the lowest power budget (25 pJ/bit) at 60 GHz reported till date.

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