ESD protection: design and layout issues for VLSI circuits
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Industry Applications
- Vol. 25 (1) , 41-47
- https://doi.org/10.1109/28.18867
Abstract
The electrostatic discharge (ESD) design issues for input, output, and power bus protection of metal-oxide semiconductor very-large-scale integration (VLSI) devices are reviewed. For input pins, the critical layout techniques that determine primary and secondary protection circuits are reported. For output pins, the effective use of the output buffer itself as a protection circuit is discussed. An effective primary circuit for rapidly discharging large amounts of stress current is a thick-oxide device with optimized layout. This device with a grounded source diffusion can provide up to 6 kV of ESD protection for the human body stress model. Some of the recent advanced process features for enhancement of VLSI circuit reliability are presented, as well as their impact on the protection circuit design and layout.Keywords
This publication has 3 references indexed in Scilit:
- ESD Phenomena and Protection Issues in CMOS Output BuffersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- NMOS protection circuitryIEEE Transactions on Electron Devices, 1985
- ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms8th Reliability Physics Symposium, 1985