An architecture for WSI rapid prototyping
- 1 April 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer
- Vol. 25 (4) , 71-75
- https://doi.org/10.1109/2.129054
Abstract
Wafer-scale integration architecture for rapid prototyping (WARP), a generalized architecture for rapid prototyping, is discussed. The primary goal of rapid prototyping is to map one of several members of a class of algorithms using a single-wafer architecture. The wafer can be personalized for the algorithm by either soft or hard-restructuring. The WARP wafer consists of an array of two types of cells specifically defined for this architecture: the universal multiply-subtract-add (UMSA) cell and the universal nonlinear (UNL) cell. Reconfiguration of the algorithms in the presence of defects, a harvesting probability model and yield, and wafer-scale testing and test facilities are described.Keywords
This publication has 2 references indexed in Scilit:
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