Gate length scaling and threshold voltage control of double-gate MOSFETs
- 11 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 719-722
- https://doi.org/10.1109/iedm.2000.904419
Abstract
In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling between the body and drain. Lateral S/D doping abruptness requirements for gate length scaling are examined. V/sub T/ control will be challenging as a single gate material for both NMOS and PMOS devices cannot provide low yet symmetrical V/sub T/'s. CMOS integration will thus require dual gate workfunction tuning, channel doping, or asymmetrical double-gates to adjust V/sub T/. Advantages of using alternative channel materials to facilitate scaling are investigated.Keywords
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