A fault analysis method for synchronous sequential circuits
- 4 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A method of fault analysis for test generation and fault diagnosisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause AnalysisIEEE Transactions on Computers, 1980
- Fault Detection in Redundant CircuitsIEEE Transactions on Electronic Computers, 1967