A 1Mb DRAM with 3-dimensional stacked capacitor cells
- 1 January 1985
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. XXVIII, 250-251
- https://doi.org/10.1109/isscc.1985.1156775
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- An experimental 1Mb DRAM with on-chip voltage limiterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Quadruply self-aligned stacked high-capacitance RAM using Ta2O5high-density VLSI dynamic memoryIEEE Transactions on Electron Devices, 1982
- A 5-V Only 16-kbit Stacked-Capacitor MOS RAMIEEE Journal of Solid-State Circuits, 1980