Influence of gate length on ESD-performance for deep sub micron CMOS technology

Publisher Website

20 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/eosesd.1999.818995

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

ESD protection methodology for deep-sub-micron CMOS
Microelectronics Reliability, 1998
Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters
IEEE Transactions on Electron Devices, 1991