Test compaction for sequential circuits
- 1 January 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 11 (2) , 260-267
- https://doi.org/10.1109/43.124404
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Test scheduling and control for VLSI built-in self-testIEEE Transactions on Computers, 1988
- An Effective Test Generation System for Sequential CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- SMART And FAST: Test Generation for VLSI Scan-Design CircuitsIEEE Design & Test of Computers, 1986
- The Complexity of Fault Detection Problems for Combinational Logic CircuitsIEEE Transactions on Computers, 1982
- Polynomially Complete Fault Detection ProblemsIEEE Transactions on Computers, 1975