An 85-MHz fourth-order programmable IIR digital filter chip
- 1 January 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 27 (2) , 175-183
- https://doi.org/10.1109/4.127340
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Pipelined VLSI recursive filter architectures using scattered look-ahead and decompositionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 100 MHz 40-tap programmable FIR filter chipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimized bit level architectures for IIR filteringPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 65 MHz 16-tap FIR filter chip with on-chip video delay linesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Dynamic storage performance of two cyanine dye films and optimization design for a recordable compact disk.Applied Optics, 2000
- Finite word effects in pipelined recursive filtersIEEE Transactions on Signal Processing, 1991
- Bit-Level systolic architectures for high performance IIR filteringJournal of Signal Processing Systems, 1989
- Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decompositionIEEE Transactions on Acoustics, Speech, and Signal Processing, 1989
- Parallel bit-level pipelined VLSI designs for high-speed signal processingProceedings of the IEEE, 1987
- Virtual Grid Symbolic LayoutPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981