Characterization of an n-p-n structure under ESD stress and proposed electrical model
- 1 April 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 37 (4) , 1111-1120
- https://doi.org/10.1109/16.52450
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Thermal response of integrated circuit input devices to an electrostatic energy pulseIEEE Transactions on Electron Devices, 1987
- Input ESD Protection Networks for Fineline NMOS - Effects of Stressing Waveform and Circuit Layout8th Reliability Physics Symposium, 1986
- Optimized ESD protection circuits for high-speed MOS/VLSIIEEE Journal of Solid-State Circuits, 1985
- ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms8th Reliability Physics Symposium, 1985