A Submicrometer Megabit DRAM Process Technology Using Trench Capacitors
- 1 February 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (1) , 130-136
- https://doi.org/10.1109/jssc.1985.1052285
Abstract
This paper describes guidelines for developing a 1-4-Mbit DRAM process, and device/process technologies for fabricating an experimental 1-Mbit DRAM. A single transistor cell combined with a trench capacitor and on-chip ECC technologies has the potential to realize a cell size of 10 /spl mu/m/sup 2/ without degrading soft error immunity. A depletion trench capacitor, submicrometer n-well CMOS process, Mo-poly gate, and sub-micrometer pattern formation technologies are developed, and an experimental 1-Mbit DRAM with a cell size of 20 /spl mu/m/sup 2/ is successfully developed by using these technologies.Keywords
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