Fast timing-driven partitioning-based placement for island style FPGAs
- 2 March 2004
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- Minimizing interconnection delays in array-based FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Timing-driven placement for hierarchical programmable logic devicesPublished by Association for Computing Machinery (ACM) ,2001
- Timing-driven routing for symmetrical array-based FPGAsACM Transactions on Design Automation of Electronic Systems, 2000
- An architecture-driven metric for simultaneous placement and global routing for FPGAsPublished by Association for Computing Machinery (ACM) ,2000
- FPGA routing architecturePublished by Association for Computing Machinery (ACM) ,1999
- Architecture and CAD for Deep-Submicron FPGASPublished by Springer Nature ,1999
- Performance-driven simultaneous placement and routing for FPGA'sIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998
- Partitioning-based standard-cell global placement with an exact objectivePublished by Association for Computing Machinery (ACM) ,1997
- Timing driven placement for large standard cell circuitsPublished by Association for Computing Machinery (ACM) ,1995