Timing constraints for wave-pipelined systems
- 1 August 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 13 (8) , 987-1004
- https://doi.org/10.1109/43.298035
Abstract
Wave-pipelining is a timing methodology used in digital systems to achieve maximal rate operation. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic and maximizing the utilization of the logic without inserting registers. This paper presents a timing constraint formulation for the correct clocking of wave-pipelined systems. Both single- and multiple-stage systems including feedback are considered. Based on the formulation of this paper, several important new results are presented relating to performance limits of wave-pipelined circuits. These results include the specification of distinct and disjoint regions of valid operation dependent on the clock period, intentional clock skew, and the global clock latency. Also, implications and motivations for the use of accurate delay models and exact timing analysis in the determination of combinational logic delays are given, and an analogous relationship between the multi-stage system and the single-stage system in terms of performance limits is shown. The minimum clock period is obtained by clock skew optimization formulated as a linear program. In addition, important special cases are examined and their relative performance limits are analyzed.Keywords
This publication has 16 references indexed in Scilit:
- CMOS sampler with 1 Gbit/s bandwidth and 25 ps resolutionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Wave Pipelining: Theory and CMOS ImplementationPublished by Springer Nature ,1994
- Clock period minimization with wave pipeliningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Designing high-performance digital circuits using wave pipelining: algorithms and practical experiencesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequencyIEEE Journal of Solid-State Circuits, 1992
- Valid clocking in wavepipelined circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Placement for clock period minimization with multiple wave propagationPublished by Association for Computing Machinery (ACM) ,1991
- A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architectureIEEE Journal of Solid-State Circuits, 1991
- Maximum-rate pipeline systemsPublished by Association for Computing Machinery (ACM) ,1969
- The Maximum Rate AccumulatorIEEE Transactions on Electronic Computers, 1966