Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
- 28 July 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 336-345
- https://doi.org/10.1109/isca.2005.53
Abstract
No abstract availableThis publication has 14 references indexed in Scilit:
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