Carry-save architectures for high-speed digital signal processing

This publication has 19 references indexed in Scilit:

• CMOS digital adaptive decision feedback equalizer chip for multilevel QAM digital radio modems
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• A digital interpolation filter chip with 32 programmable coefficients for 80 MHz sampling frequency
  IEEE Journal of Solid-State Circuits, 1991
• Programmable 2D linear filter for video applications
  IEEE Journal of Solid-State Circuits, 1990
• Generalized signed-digit number systems: a unifying framework for redundant number representations
  IEEE Transactions on Computers, 1990
• Bit-Level systolic architectures for high performance IIR filtering
  Journal of Signal Processing Systems, 1989
• Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition
  IEEE Transactions on Acoustics, Speech, and Signal Processing, 1989
• A 2- mu m CMOS digital adaptive equalizer chip for QAM digital radio modems
  IEEE Journal of Solid-State Circuits, 1988
• Advanced Time- and Frequency-Domain Adaptive Equalization in Multilevel QAM Digital Radio Systems
  IEEE Journal on Selected Areas in Communications, 1987
• A Pipelined 330-MHz Multiplier
  IEEE Journal of Solid-State Circuits, 1986
• A note on 'free accumulation' in VLSI filter architectures
  IEEE Transactions on Circuits and Systems, 1985