A Network Comparison Algorithm for Layout Verification of Integrated Circuits
- 1 April 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 3 (2) , 135-141
- https://doi.org/10.1109/tcad.1984.1270067
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
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