Creator: new advanced concepts in concurrent simulation
- 1 June 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 13 (6) , 786-795
- https://doi.org/10.1109/43.285237
Abstract
Creator is a concurrent simulator for design verification and fault simulation of large circuits that highly integrates several traditional and innovative techniques. This is achieved by the introduction of a minimal information concept. Traditional techniques derived from previous works are Multiple List Traversal (MLT), trigger inhibition, fraternal event processing, list events, acid clock suppression, whereas the new ideas are function lists and evaluation functions, persistence time, positioning algorithm, evaluation triggering algorithm, combination of Single List Traversal (SLT) and MLT, and the implementation of transport delay in fault simulation. Generally the concurrent algorithm increases in complexity and the implementations grow in size and lose in performance as soon as higher abstraction levels are added beyond the gate one. To overcome this limitation, all the Creator's techniques are not related to a specific abstraction level and lead to an intrinsic multilevel concurrent fault simulator. Experimental results are reported to compare Creator with our previous simulator and the state-of-the-art commercial simulator Verifault-XL on several platformsKeywords
This publication has 11 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Periodic signal suppression in a concurrent fault simulatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The Comparative and Concurrent Simulation of discrete-event experimentsJournal of Electronic Testing, 1992
- PROOFS: a fast, memory-efficient sequential circuit fault simulatorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- An accurate timing model for gate-level simulation of MOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- Differential fault simulation for sequential circuitsJournal of Electronic Testing, 1990
- MOZART: a concurrent multilevel simulatorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Advances in Concurrent Multilevel SimulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Event manipulation for discrete simulations requiring large numbers of eventsCommunications of the ACM, 1978
- Concurrent simulation of nearly identical digital networksComputer, 1974