A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC

23 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 314-315
https://doi.org/10.1109/isscc.1996.488633

Abstract

This 1.2 /spl mu/m, 33 mW analog-to-digital converter (ADC) demonstrates a family of power reduction techniques including a commutated feedback capacitor switching (CFCS), sharing of the second stage of an op amp between adjacent stages of a pipeline, reusing the first stage of an op amp as the comparator pre-amp, and exploiting parasitic capacitance as common-mode feedback capacitors.

Keywords

CAPACITORS
OPERATIONAL AMPLIFIERS
FEEDBACK
PIPELINES
PARASITIC CAPACITANCE
SAMPLING METHODS
VOLTAGE
CMOS TECHNOLOGY
ANALOG-DIGITAL CONVERSION
HIGH-RESOLUTION IMAGING

This publication has 2 references indexed in Scilit:

A mismatch independent DNL-pipelined analog to digital converter
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
A pipelined A/D conversion technique with near-inherent monotonicity
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1995