Coplanar Integration of Lattice-Mismatched Semiconductors with Silicon by Wafer Bonding Ge/Si[sub 1−x]Ge[sub x]/Si Virtual Substrates

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Abstract
We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding Ge/Si1−xGex/SiGe/Si1−xGex/Si virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator (GOI) have been identified and solved, resulting in the transfer of epitaxial Ge/SiO2Ge/SiO2 to a Si wafer. We found that planarization of Ge virtual substrates was a key limiting factor in the transfer process. To circumvent this problem, an oxide layer was first deposited on the Ge film before planarization using a standard oxide chemical mechanical planarization process. The GOI structure was created using H2H2 -induced layer exfoliation (Smartcut™) and a buried Si0.4Ge0.6Si0.4Ge0.6 etch-stop layer, which was used to subsequently remove the surface damage with a hydrogen peroxide selective etch. After selective etching, the crosshatched surface morphology of the original virtual substrate was preserved with roughness of 25×25 μm25×25 μm scale and a 1×1 μm1×1 μm scale roughness of <1.4 nm.<1.4 nm. Using an etch-stop layer, the transferred device layer thickness is defined epitaxially allowing for future fabrication of ultrathin GOI as well as III-V films directly on large-diameter Si wafers. © 2004 The Electrochemical Society. All rights reserved.

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