The TLB slice-a low-cost high-speed address translation mechanism
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 355-363
- https://doi.org/10.1109/isca.1990.134546
Abstract
The MIPS R6000 microprocessor relies on a new type of translation lookaside buffer, called a TLB slice, which is less than one-tenth the size of a conventional TLB and as fast as one multiplexer delay, yet has a high enough hit rate to be practical. The fast translation makes it possible to use a physical cache without adding a translation stage to the processor's pipeline. The small size makes it possible to include address translation on-chip, even in a technology with a limited number of devices. The key idea behind the TLB slice is to have both a virtual tag and a physical tag on a physically indexed cache.<>Keywords
This publication has 10 references indexed in Scilit:
- A simulation study of two-level cachesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Characteristics of performance-optimal multi-level cache hierarchiesPublished by Association for Computing Machinery (ACM) ,1989
- Organization and performance of a two-level virtual-real cache hierarchyPublished by Association for Computing Machinery (ACM) ,1989
- System design using the MIPS R3000/3010 RISC chipsetPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- Precision architectureComputer, 1989
- Design Decisions in SPURComputer, 1986
- An in-cache address translation mechanismACM SIGARCH Computer Architecture News, 1986
- Cache MemoriesACM Computing Surveys, 1982
- Virtual MemoryACM Computing Surveys, 1970
- Study of "Look-Aside" MemoryIEEE Transactions on Computers, 1969