A 150ns CMOS 64K EPROM using N-well technology
- 1 January 1982
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. XXV, 182-183
- https://doi.org/10.1109/isscc.1982.1156423
Abstract
THE STRONG NEED for low power, high density, high performance CMOS EPROMs has been established by the evolution of faster and denser low power microprocessors, due to their de pendence on convenient program storage memories. This requirement was met initially bl the 4K CMOS EPROM1 and later by the 16K CMOS EPROM using P-well CMOS technology. This paper will discuss an SK x 8 CMOS EPROM* using double-polysilicon, P-sub N-well CMOS technology 4 ; Figure I. Memory cells have been fabricated on the P-type substrate and surrounded by a guard ring to avoid any latchup phenomena which may be caused by carrier injection into the bulk of the cell array during programming. CMOS peripheral circuits have been used to achieve fast access times and sub-microampere standby current.Keywords
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