Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication
- 1 February 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 368-609
- https://doi.org/10.1109/isscc.2007.373447
Abstract
Two chips communicate over a capacitively-coupled I/O link at 1.8Gb/s/ch. Channels are placed on a 36mum pitch. 144 channels operate simultaneously for an aggregate bandwidth of 260Gb/s, or 430Gb/s/mm2 in 0.18mum CMOS. Measured energy consumption is 3.0pJ/b and BER is -15. Electronic alignment and crosstalk rejection allow reliable I/O for practical implementationKeywords
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