A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link
- 26 December 2006
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 42 (1) , 111-122
- https://doi.org/10.1109/jssc.2006.886554
Abstract
A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13Keywords
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