Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs

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Abstract
The current conduction process through a nanowire wrap-around-gate, ∼50 nm channel diameter, silicon MOSFET has been investigated and compared with a ∼2 μm wide slab, ∼200 nm thick silicon (SOI) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and gate oxide thickness. The experimental characteristics of the nanowire and planar MOSFETs were compared with theoretical simulation results based on semi-empirical carrier mobility models. The SOI nanowire MOS devices were fabricated through interferometric lithography in combination with conventional I-line lithography. A significant increase (∼3×) in current density was observed in the nanowire devices compared to the planar devices. A number of parameters such as carrier confinement, effects of parallel and transverse field-dependent mobilities, and carrier scattering due to Coulomb effects, acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The electron mobility in the nanochannel increases to ∼1200 cm2/V s compared to ∼400 cm2/V s for a wide slab planar device of similar channel length. Experiments also show that the application of the channel potential from three sides in the nanowire structure dramatically improves the subthreshold slope characteristics.