Reasoning about VHDL and VHDL-AMS using denotational semantics

This publication has 4 references indexed in Scilit:

• A formal method for specification and refinement of real-time systems
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• A refinement calculus for the synthesis of verified hardware descriptions in VHDL
  ACM Transactions on Programming Languages and Systems, 1997
• A simple denotational semantics, proof theory and a validation condition generator for unit-delay VHDL
  Formal Methods in System Design, 1995
• Abstract interpretation: a unified lattice model for static analysis of programs by construction or approximation of fixpoints
  Published by Association for Computing Machinery (ACM) ,1977