A review and projection of semiconductor components for digital storage
- 1 January 1975
- journal article
- review article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 63 (8) , 1136-1147
- https://doi.org/10.1109/proc.1975.9906
Abstract
Evolution of present integrated-circuit technology over the remainder of the decade should result in semiconductor memories which are competitive with moving-surface memories and other alternatives in many digital storage applications requiring 107-1010bits capacity. This paper considers MOS, MNOS, CCD, and bipolar component approaches to this objective. Cost, reliability, and power consumption, as affected by technological choices, receive attention. Alternative device technologies and circuit designs are examined. The one-transistor MOS RAM is seen to have potential for considerable growth. Packaging and interconnection methods for low cost and high reliability are considered; evolution of existing techniques is expected. Reliability and maintainability characteristics are seen to be controlled by device technology, component organization, and packaging characteristics. Testing, screening, and error-correction techniques are considered. Projections of component characteristics are extended to outline hypothetical designs for 4-million-bit and 256-million-bit storage systems which might be built by 1980. Features include 64K-bit MOS RAM components on die of area under 100 mm2, system selling price of 40 m¢/bit, power consumption well below 1 µW/bit, system MTBF greater than 105h, and physical density on the order of 16000 bits/ cm3. The basis for projected parameters is explained. The advantages and drawbacks of these hypothetical systems relative to moving-surface magnetic storage systems are outlined.Keywords
This publication has 38 references indexed in Scilit:
- CCD memory arrays with fast access by on-chip decodingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1974
- Nonvolatile block-oriented RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1974
- Design of a high-performance 1024-B switched capacitor p-channel IGFET memory chipIEEE Journal of Solid-State Circuits, 1973
- A 1-mil/SUP 2/ single-transistor memory cell in n silicon-gate technologyIEEE Journal of Solid-State Circuits, 1973
- CCD memory optionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- Electrically reprogrammable nonvolatile semiconductor memoryIEEE Journal of Solid-State Circuits, 1972
- MNOS memory transistors in simple memory arraysIEEE Journal of Solid-State Circuits, 1972
- MAS-ROM-electrically reprogrammable ROM with decoderIEEE Journal of Solid-State Circuits, 1972
- Storage array and sense/refresh circuit for single-transistor memory cellsIEEE Journal of Solid-State Circuits, 1972
- An integrated metal-nitride-oxide-silicon (MNOS) memoryProceedings of the IEEE, 1969