Combinational equivalence checking using satisfiability and recursive learning
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 145-149
- https://doi.org/10.1109/date.1999.761110
Abstract
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. Previously, several approaches have been proposed for solving this problem. Still, the hardness of the problem and the ever-growing complexity of logic circuits motivates studying and developing alternative solutions. In this paper we study the application of Boolean satisfiability (SAT) algorithms for solving the combinational equivalence checking (CEC) problem. Although existing SAT algorithms are in general ineffective for solving CEC, in this paper we show how to improve SAT algorithms by extending and applying recursive learning techniques to the analysis of instances of SAT. This in turn provides a new alternative and competitive approach for solving CEC. Preliminary experimental results indicate that the proposed improved SAT algorithm can be useful for a large variety of instances of CEC, in particular when compared with pure BDD-based approaches.Keywords
This publication has 15 references indexed in Scilit:
- Functional comparison of logic designs for VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Logic verification using binary decision diagrams in a logic synthesis environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Sequential circuit design using synthesis and optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Verification of large synthesized designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- GRASP-A new search algorithm for satisfiabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlistsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- Combinational test generation using satisfiabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996
- An efficient equivalence checker for combinational circuitsPublished by Association for Computing Machinery (ACM) ,1996
- Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis EnvironmentProceedings of the 39th conference on Design automation - DAC '02, 1995
- Test pattern generation using Boolean satisfiabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992