A temperature- and process-tolerant 64K EEPROM
- 1 October 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (5) , 979-985
- https://doi.org/10.1109/jssc.1985.1052424
Abstract
A 64K EEPROM is described with emphasis on the circuit techniques used to achieve extended temperature operation. The core architecture is considered and a suitable byte layout which eliminates possible punchthrough in the memory cell is shown. A feedback-controlled substrate bias generator is described which delivers -1.0 V/spl plusmn/0.05 V and reduces significantly field transistor leakages. In addition, a /spl plusmn/1% stable voltage reference is shown to accurately control the programming voltage for the memory array to 20 V/spl plusmn/1 V over the full military temperature range (-55/spl deg/-+125/spl deg/C) and /spl plusmn/10% power-supply variation. A process-insensitive write timing pulse trimmed by E2 fuses is discussed, as is the PAGE-MODE WRITE circuitry in relation to the bitline latches.Keywords
This publication has 3 references indexed in Scilit:
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- A 5V-only EEPROM with internal program/erase controlPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
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