A modeling and circuit reduction methodology for circuit simulation of DRAM circuits
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- A newly designed planar stacked capacitor cell with high dielectric constant film for 256 Mbit DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 34 ns 256 Mb DRAM with boosted sense-ground schemePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analog hardware description languagesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 32-bank 256-Mb DRAM with cache and TAGIEEE Journal of Solid-State Circuits, 1994
- 256-Mb DRAM circuit technologies for file applicationsIEEE Journal of Solid-State Circuits, 1993
- A 30-ns 256-Mb DRAM with a multidivided array structureIEEE Journal of Solid-State Circuits, 1993
- Macromodeling of integrated circuit operational amplifiersIEEE Journal of Solid-State Circuits, 1974