A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 403
- https://doi.org/10.1109/test.1991.519700
Abstract
No abstract availableKeywords
This publication has 13 references indexed in Scilit:
- Delay test generation for synchronous sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Synthesis of delay fault testable combinational logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Arrangement of latches in scan-path design to improve delay fault coveragePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design of scan-testable CMOS sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On the design of path delay fault testable combinational circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Synthesis of combinational logic circuits for path delay fault testabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Robust delay-fault test generation and synthesis for testability under a standard scan design methodologyPublished by Association for Computing Machinery (ACM) ,1991
- Transition Fault SimulationIEEE Design & Test of Computers, 1987
- A Heuristic Algorithm for the Testing of Asynchronous CircuitsIEEE Transactions on Computers, 1971