Characterization of intrinsic a-Si:H in p-i-n devices by capacitance measurements: Theory and experiments

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Abstract
A technique has been developed for characterizing the intrinsic layer in a‐Si:H p‐i‐n structures. The method is based on the measurement of the differential capacitance under forward bias, i.e., with injection of free carriers in the intrinsic layer. In these conditions, capacitance is extremely dependent on charges trapped in the band‐gap defects. Measurements were performed on several p‐i‐n samples, in a wide range of frequencies and voltages. All the samples showed the same trend: Capacitance diminished with increasing signal frequency and increased with forward applied voltage. An analytical model explains the obtained behavior. In particular, the model shows that the band‐tail contribution to capacitance decreases slowly with frequency, while deeper defects are effective only below 100 Hz. At higher frequencies, trapping phenomena play a lesser and lesser role in the measurement while depletion charge becomes relevant and the measured capacitance tends to its asymptotic junction value (i.e., the ratio dielectric constant/thickness of the p‐i‐n). The model predicts a high sensitivity to defect distribution in the gap of the intrinsic layer, thus allowing an effective characterization of the semiconductor material as is in the actual device. Up to 1017 cm−3 defects have been detected via the capacitance technique, presumably located in the portion of the intrinsic layer closest to the p/i interface. The origin of such a large amount of defects can be related to the presence of inhomogeneities due to the interfaces in the p‐i‐n device. These defects behave as free‐carrier traps, and do not affect the recombination mechanism. A picture of the electronic defect distribution in the device material is finally proposed which accounts for both midgap neutral dangling bonds and shallower charged defects.