A low-power, high-performance, 1024-point FFT processor
- 1 March 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 34 (3) , 380-387
- https://doi.org/10.1109/4.748190
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- A 200 MIPS single-chip 1 k FFT processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An application specific DSP chip set for 100 MHz data ratesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An energy-efficient single-chip FFT processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A real time FFT chip set: architectural issuesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design and implementation of a 1024-point pipeline FFT processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1998
- A fast single-chip implementation of 8192 complex point FFTIEEE Journal of Solid-State Circuits, 1995
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992
- FFTs in external or hierarchical memoryThe Journal of Supercomputing, 1990
- Fast Fourier transform of externally stored dataIEEE Transactions on Audio and Electroacoustics, 1969
- A method for computing the fast Fourier transform with auxiliary memory and limited high-speed storageIEEE Transactions on Audio and Electroacoustics, 1967