A 10-bit 5-Msample/s CMOS two-step flash ADC
- 1 April 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (2) , 241-249
- https://doi.org/10.1109/4.18582
Abstract
A 10-b, 5Msample/s, two-step flash A/D converter fabricated in a 1.6 mu m CMOS process is described. The architecture is based on a resistor string and capacitor arrays and was developed to overcome the disadvantages of the previous approaches, namely flash, pipelined, and classical two-step converters. With minimal capacitor matching requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize charge-injection errors the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000, and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54 kmil/sup 2/. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string.Keywords
This publication has 9 references indexed in Scilit:
- An 8b 20mhz Cmos Half-Flash A/D ConverterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A 10b 20mhz Two-Step Parallel ADC with Internal S/HPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- An 8-bit high-speed CMOS A/D converterIEEE Journal of Solid-State Circuits, 1986
- An 8-MHz CMOS subranging 8-bit A/D converterIEEE Journal of Solid-State Circuits, 1985
- A CMOS 8-Bit High-Speed A/D Converter ICIEEE Journal of Solid-State Circuits, 1985
- Full-speed testing of A/D convertersIEEE Journal of Solid-State Circuits, 1984
- A precision variable-supply CMOS comparatorIEEE Journal of Solid-State Circuits, 1982
- Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converterIEEE Journal of Solid-State Circuits, 1979
- All-MOS charge redistribution analog-to-digital conversion techniques. IIEEE Journal of Solid-State Circuits, 1975