Architectural exploration and optimization of local memory in embedded systems
- 22 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10801820,p. 90-97
- https://doi.org/10.1109/isss.1997.621680
Abstract
Embedded processor-based systems allow for the tailoring of the on-chip memory architecture based on application-specific requirements. We present an analytical strategy for exploring the on-chip memory architecture for a given application, based on a memory performance estimation scheme. The analytical technique has the important advantage of enabling a fast evaluation of candidate memory architectures in the early stages of system design. Our experiments demonstrate that our estimations closely follow the actual simulated performance at significantly reduced run times.Keywords
This publication has 9 references indexed in Scilit:
- Memory organization for improved data cache performance in embedded processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An algorithm for array variable clusteringPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Efficient utilization of scratch-pad memory in embedded processor applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Library mapping for memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Architectural exploration and optimization of local memory in embedded systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 1995 high level synthesis design repositoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Foreground memory management in data path synthesisInternational Journal of Circuit Theory and Applications, 1992
- A data locality optimizing algorithmPublished by Association for Computing Machinery (ACM) ,1991
- An analytical cache modelACM Transactions on Computer Systems, 1989