SPIDER: capacitance modelling for VLSI interconnections

1 December 1988

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Vol. 7 (12) , 1221-1228
https://doi.org/10.1109/43.16800

Abstract

An efficient method is presented to model the parasitic capacitance of VLSI interconnections. It is valid for conductors in a stratified medium which is considered to be a good approximation for the Si-SiO/sub 2/ system of which ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a 'spider' of edges. The model has very low complexity as compared to previously presented models and achieves a high degree of precision within the range of validity of the stratified medium.

Keywords

This publication has 8 references indexed in Scilit:

Capacitance coefficients for VLSI multilevel metallization lines
IEEE Transactions on Electron Devices, 1987
On the parasitic capacitances of multilevel parallel metallization lines
IEEE Transactions on Electron Devices, 1985
VLSI parasitic capacitance determination by flux tubes
IEEE Circuits & Systems Magazine, 1982
Capacitances of a planar multiconductor configuration on a dielectric substrate by a mixed order finite-element method
IEEE Transactions on Circuits and Systems, 1976
Capacitance models for integrated circuit metallization wires
IEEE Journal of Solid-State Circuits, 1975
Calculation of the capacitance coefficients of planar conductors on a dielectric surface
IEEE Transactions on Circuit Theory, 1973
Efficient Capacitance Calculations for Three-Dimensional Multiconductor Systems
IEEE Transactions on Microwave Theory and Techniques, 1973
Calculation of Capacitance Coefficients for a System of Irregular Finite Conductors on a Dielectric Sheet
IEEE Transactions on Microwave Theory and Techniques, 1971