Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks

An experimental and modeling study of charge trapping related threshold voltage shifts in ${\mathrm{Al}}_2{\mathrm{O}}_3$ and ${\mathrm{HfO}}_2$ n-type field effect transistors $\mathrm{(n}\mathrm{FET})$ is reported. The dependence of threshold voltage, subthreshold slope, and gate leakage currents on stressing time and injected charge carrier density are investigated as a function positive bias stress voltage and temperature. Based on experimental data, a model for trapping of charges in the existing traps is developed. The model is similar to ${\mathrm{SiO}}_2$ charge trapping models with one exception. Unlike ${\mathrm{SiO}}_2$ models, the model assumes a continuous distribution in trapping capture cross sections. The model predicts that threshold voltage would increase with a power law dependence on stressing time and injected charge carrier density ${\mathrm{(N}}_{\mathrm{inj}})$ in the initial stages of stressing. The model calculates threshold voltage shifts as a function of stress time and $N_{\mathrm{inj}},$ thereby provides estimates of threshold voltage shifts after 10 years lifetime. It also provides insights into the nature of traps by estimating trapping capture cross sections. The calculated results are shown to be consistent with both ${\mathrm{Al}}_2{\mathrm{O}}_3$ and ${\mathrm{HfO}}_2$ data over several decades of stressing time and $N_{\mathrm{inj}}.$ Using the model, a comparison between ${\mathrm{Al}}_2{\mathrm{O}}_3$ and ${\mathrm{HfO}}_2$ is made. In addition, the model is compatible with charge trapping data reported by other research groups.