Enabling technologies for forming and contacting shallow junctions in Si: HF-vapor cleaning and selective epitaxial growth of Si and SiGe

Future generation devices with critical dimensions of less than 130 nm will have source/drain areas with junction depths of less than about 70 nm and a sheet resistance of around 3 Ω/sq. Conventional technologies used to form and contact such shallow and low resistance source/drain areas are concluded to no longer be feasible in manufacturing. Elevated source/drain technology is shown to be very attractive for manufacturing sub-130 nm devices. In this article we describe two critical processes to form such elevated source/drains. First, a novel HF-vapor clean chemistry for native oxide removal is described. The etch chemistry uses acetic acid vapor as a catalyst to initiate and control etching with HF vapor. Excellent repeatability and selectivity are achieved. Second, in situ doped selective epitaxial growth (SEG) of Si and SiGe is addressed. The advantages of adding Ge to the epitaxial film are discussed. Issues like microloading and facet formation are also discussed and are demonstrated as solvable. Vacuum integration of the above two mentioned processes eliminates the need for a high temperature ${\mathrm{H}}_{\mathrm{2}}$ bake. The elimination of the ${\mathrm{H}}_{\mathrm{2}}$ bake and the addition of Ge to enable SEG at lower temperatures are demonstrated to substantially decrease the thermal budget, increase throughput, and eliminate queue time in the factory. These improvements make elevated source/drain technology technically and economically feasible for the manufacturing of 130–70 nm devices.