A concurrent operating CDRAM for low cost multi-media

1 January 1993

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 61-62
https://doi.org/10.1109/vlsic.1993.920537

Abstract

This paper describes a concurrent operating cache DRAM (CDRAM) for low cost multi-media systems, in which the program and graphic data coexist in the main memory. The concurrent operation of the DRAM and SRAM completely removes the idle cycles. As a result, the average access time is equal to the SRAM access time of 6.5 ns with 0.6 /spl mu/m CMOS process. The flash write and direct read/write are also useful for the multi-media systems.

Keywords

DRAM CHIPS
CACHE MEMORIES
CMOS INTEGRATED CIRCUITS, MEMORY
MULTIMEDIA SYSTEMS
SRAM CHIPS

This publication has 2 references indexed in Scilit:

500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
A 100-MHz 4-Mb cache DRAM with fast copy-back scheme
IEEE Journal of Solid-State Circuits, 1992