Achieving uniform nMOS device power distribution for sub-micron ESD reliability
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 131-134
- https://doi.org/10.1109/iedm.1992.307325
Abstract
The ESD reliability of the advanced sub-micron technologies is a major concern because of the shallow LDD junctions. This paper will show that by achieving uniform power distribution during the entire ESD event in a large multi-finger nMOS device of 0.6 mu m technology, protection levels in excess of 10 kV can be realized. The evidence of this uniform power distribution resulting from the multi-finger parasitic npn turn-on is shown through an emission microscopy analysis.Keywords
This publication has 5 references indexed in Scilit:
- ESD phenomena in graded junction devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- 0.5 micron CMOS for high performance at 3.3 VPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- New algorithms for circuit simulation of device breakdownIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistorsIEEE Transactions on Electron Devices, 1988
- ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms8th Reliability Physics Symposium, 1985