The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors
- 1 January 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 35 (12) , 2140-2145
- https://doi.org/10.1109/16.8788
Abstract
No abstract availableKeywords
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