Systolic arrays for Viterbi processing in communication systems with a time-dispersive channel

This publication has 7 references indexed in Scilit:

• Implementation of a Viterbi Processor for a Digital Communications System with a Time-Dispersive Channel
  IEEE Journal on Selected Areas in Communications, 1986
• An Adaptive Maximum Likelihood Sequence Estimation Technique for Wideband HF Communications
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1982
• Why systolic architectures?
  Computer, 1982
• Microprocessor based implementation and testing of a simple Viterbi detector
  Canadian Electrical Engineering Journal, 1981
• Adaptive Maximum-Likelihood Receiver for Carrier-Modulated Data-Transmission Systems
  IEEE Transactions on Communications, 1974
• The viterbi algorithm
  Proceedings of the IEEE, 1973
• Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference
  IEEE Transactions on Information Theory, 1972