Radiation Hardened 64-BIT CMOS/SOS RAM
- 1 December 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 23 (6) , 1728-1731
- https://doi.org/10.1109/tns.1976.4328569
Abstract
Radiation hardening procedures have been implemented in design, analysis and fabrication of a 64-bit CMOS/SOS RAM. The resultant circuit is a moderately complex (714 transistor), dielectrically isolated integrated circuit which features high performance and high radiation tolerance. Typical electrical parameters include 120 nsec read-access time and 1μwatt/bit standby power dissipation. The SOS construction minimizes radiation-induced transient photocurrents while a hardened gate insulator provides immunity to total dose effects. Transient radiation upset levels exceed 3 × 1010 rads(Si)/sec for short (≤ 50 ns) pulses and ionizing dose hardness exceeds 106 rads(Si). A neutron fluence of 3.65 × 1014 n/cm2 had no effect on circuit operation beyond that expected from the ionizing radiation alone.Keywords
This publication has 3 references indexed in Scilit:
- Self Aligned Radiation Hard CMOS/SOSIEEE Transactions on Nuclear Science, 1976
- Investigation of Radiation Effects and Hardening Procedures for CMOS/SOSIEEE Transactions on Nuclear Science, 1975
- CMOS/SOS NAND Gate Sapphire Photocurrent CompensationIEEE Transactions on Nuclear Science, 1975