Switch-level modeling of transistor-level stuck-at faults

This publication has 16 references indexed in Scilit:

• Transistor Fault Coverage for Self-Testing CMOS Checkers
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Efficient modeling of switch-level networks containing undetermined logic node states
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Modeling of intermediate node states in switch-level networks
  Published by Association for Computing Machinery (ACM) ,1994
• Exhaustive testing of stuck-open faults in CMOS combinational circuits
  IEE Proceedings E Computers and Digital Techniques, 1988
• Physical faults in MOS circuits and their coverage by different fault models
  IEE Proceedings E Computers and Digital Techniques, 1988
• COSMOS: a compiled simulator for MOS circuits
  Published by Association for Computing Machinery (ACM) ,1987
• Pseudo-Boolean Logic Circuits
  IEEE Transactions on Computers, 1986
• A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
• A Switch-Level Model and Simulator for MOS Digital Systems
  IEEE Transactions on Computers, 1984